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71107 ti pc 20070621-s00004/41807 ti pc b8-9144 no.a0081-1/14 http://onsemi.com semiconductor components industries, llc, 2013 may, 2013 lb11873 overview the lb11873 is a 3-phase brushless motor driver developed for driving the polygonal mirror motor used in plain-paper copiers and similar products. this ic can implement the circuits required for polygonal mirror motor drive (speed control and driver circuits) in a single chip. the lb11873 implements low-noise/low-vibration pwm drive by changing the current at phase switching gradually to reduce motor noise. functions ? three-phase bipolar drive (quiet direct pwm) ? pll speed control circuit ? hall sensor fg support ? dedicated external clock ? brake mode switching circuit (free running and reverse braking) ? phase lock detection output (with masking function) ? built-in current limiter, constraint protection, undervoltage protection, thermal protection, and clk line disconnection protection circuits ? input pins support 3v system microcontrollers specifications absolute maximum ratings at ta = 25 c parameter symbol conditions ratings unit supply voltage v cc max 30 v output current i o max t 500ms 1.8 a allowable power dissipation 1 pd max1 independent ic 0.9 w allowable power dissipation 2 pd max2 when mounted on a circuit board *1 2.1 w operating temperature topr -20 to +80 c storage temperature tstg -55 to +150 c *1 specified circuit board : 114.3 76.1 1.6mm 3 , glass epoxy. monolithic digital ic for polygonal mirror motors three-phase brushless motor driver orderin g numbe r : ENA0081b stresses exceeding maximum ratings may damage the device. maximum ratings are stress ratings only. functional operation above the recommended oper ating conditions is not implied. extended exposure to stresses above the recommended operating conditions may affect device reliabili ty.
lb11873 no.a0081-2/14 allowable operating ranges at ta = 25 c parameter symbol conditions ratings unit supply voltage range v cc 9.5 to 28 v 5v constant voltage output ireg 0 to -30 ma ld pin apply voltage vld 0 to 28 v ld pin output current ild 0 to 15 ma fgs pin apply voltage vfgs 0 to 28 v fgs pin output current ifgs 0 to 10 ma hb pin apply voltage vhbs 0 to 28 v hb pin output current ihbs 0 to 30 ma electrical characteristics at ta = 25 c, v cc = v m = 24v ratings parameter symbol conditions min typ max unit supply current 1 i cc 1 22 28 ma supply current 2 i cc 2 stop mode 4.0 6.0 ma 5v constant voltage output (vreg pin) output voltage vreg 4.65 5.0 5.35 v line regulation vreg1 v cc = 9.5 to 28v 80 130 mv load regulation vreg2 i o = -5 to -20ma 10 60 mv temperature coefficient vreg3 design target * 0 mv/ c output block output saturation voltage 1 v o sat1 i o = 0.5a, v o (sink) + v o (source) 1.4 1.9 v output saturation voltage 2 v o sat2 i o = 1.2a, v o (sink) + v o (source) 2.0 2.6 v output leakage current i o leak 100 a high side diode forward voltage 1 vd2-1 id = 0.5a 1.0 1.5 v high side diode forward voltage 2 vd2-2 id = 1.2a 1.5 2.0 v hall sensor amplifier block input bias current ihb 2 10 a differential input range vihin sine wave input 50 350 common-mode input voltage range vicm 1.5 vreg ? 1.0 v input offset voltage vioh design target value* -20 20 mv hall sensor bias output saturation voltage v ol (hb) ihb = 10ma 1.5 2.0 v output leakage current i l (hb) v o = v cc , stop mode 10 a fg schmitt trigger block (in1) input amplifier gain gfg design target value* 5 times input hysteresis (high low) vshl design target value* 0 mv input hysteresis (low high) vslh design target value* -10 mv hysteresis vfgl input conversion, design target value * 47 12mv pwm oscillator high-level output voltage v oh (pwm) 2.65 2.95 3.25 v low-level output voltage v ol (pwm) 0.9 1.2 1.5 v external capacitor charge current ichg vpwm = 2v -60 -45 -30 a oscillator frequency f (pwm) c = 680pf 34 khz amplitude v (pwm) 1.45 1.75 2.05 vp-p * the design specification items are design guarantees and are not measured. continued on next page.
lb11873 no.a0081-3/14 continued from preceding page. ratings unit parameter symbol conditions min typ max fgs pin output saturation voltage v ol (fgs) ifgs = 7ma 0.15 0.5 v output leakage current i l (fgs) v o = v cc 10 a csd oscillator circuit oscillator frequency f (csd) c = 0.033 f 31 hz high-level output voltage v oh (csd) 3.50 3.75 4.00 v low-level output voltage v ol (csd) 1.00 1.30 1.60 v amplitude v (csd) 2.20 2.45 2.80 vp-p external capacitor charge current ichg1 vcsd = 2v -7 -5 -3 a external capacitor discharge current ichg2 vcsd = 2v 3 5 7 a lock detection delay counts csdct1 7 clock disconnected protection counts csdct2 2 constraint protection operation counts csdct3 31 initial reset voltage vres 0.6 0.8 v phase comparator output high-level input voltage vpdh i oh = -100 a vreg - 0.2 vreg - 0.1 v low-level input voltage vpdl i ol = 100 a 0.2 0.3 v input source current ipd+ vpd = vreg/2 -0.5 ma input sink current ipd- vpd = vreg/2 1.5 ma phase lock detection output output saturation voltage v ol (ld) i ld = 10ma 0.15 0.5 v output leakage current i l (ld) v o = v cc 10 a error amplifier block input offset voltage v io (er) design target value* -10 10 mv input bias current ib (er) -1 1 a high-level output voltage v oh (er) iei = -0.1ma, no load 3.7 4.0 4.3 v low-level output voltage v ol (er) iei = 0.1ma, no load 0.7 1.0 1.3 v dc bias level vb (er) -5% vreg/2 5% v current llimiter circuit drive gain 1 gdf1 in the phase locked state 0.4 0.5 0.6 times drive gain 2 gdf2 in the unloc ked state 0.8 1.0 1.2 times llimiter voltage 1 vrf1 v cc - vm, forward mode 0.45 0.5 0.55 v llimiter voltage 2 vrf2 v cc - vm, reverse mode 0.225 0.25 0.275 v thermal shutdown circuit thermal shutdown operating temperature tsd design target value* (junction temperature) 150 170 c thermal shutdown temperature hysteresis tsd design target value* (junction temperature) 40 c low voltage protection circuit operating voltage vsdl 8.1 8.45 8.9 v hysteresis vsd 0.2 0.35 0.5 v clk pin external input frequency fi (clk) 0.1 10 khz high-level input voltage v ih (clk) 2.0 vreg v low-level input voltage v il (clk) 0 1.0 v input open voltage vio (clk) 3.0 v hysteresis vis (clk) 0.25 v high-level input current i ih (clk) vckin = vreg 115 150 a low-level input current i il (clk) vckin = 0v -220 -175 a continued on next page. note : * the design specification items are design guarantees and are not measured.
lb11873 no.a0081-4/14 continued from preceding page. ratings unit parameter symbol conditions min typ max s/s pin high-level input voltage v ih (ss) 2.0 vreg v low-level input voltage v il (ss) 0 1.0 v input open voltage vio (ss) 3.0 v hysteresis vis (ss) 0.21 0.25 0.29 v high-level input current i ih (ss) vs/s = vreg 115 150 a low-level input current i il (ss) vs/s = 0v -220 -175 a brsel pin high-level input voltage v ih (brsel) 2.0 vreg v low-level input voltage v il (brsel) 0 1.0 v input open voltage vio (brsel) 3.0 v hysteresis vis (brsel) 0.21 0.25 0.29 v high-level input current i ih (brsel) vbrsel = vreg 115 150 a low-level input current i il (brsel) vbrsel = 0v -220 -175 a package dimensions unit : mm (typ) 3235a three-phase logic truth table (the input "h" state is t he state where in+ > in-) in1 in2 in3 out1 out2 out3 h l h l h m h l l l m h h h l m l h l h l h l m l h h h m l l l h m h l s/s pin input state state high or open stop low start bresel pin input state during deceleration high or open free running low reverse braking sanyo : hsop36(375mil) (6.2) 36 1 0.8 17.8 2.7 0.3 (4.9) 10.5 0.65 0.25 (0.5) 7.9 (2.25) 2.45max 0.1 2.0 0 1.0 0.5 1.5 2.0 2.5 ? 20 0 80 60 20 40 100 0.9w 2.1w 1.18w ambient temperature, ta ? c allowable power dissipation, pd max ? w pd max ? ta specified circuit board : 114.3 76.1 1.6mm 3 glass epoxy board independent ic
lb11873 no.a0081-5/14 pin assignment hall sensor input waveforms and output current waveform (1) when the hall sensor input amplitude is small or when the input waveform slope is low 180 drive: current flows during all periods; there are on off periods (180 drive) (2) when the hall sensor input amplitude is larger or when the input waveform slope is steep in this case, periods in which drive is off will occur (the off periods vary depending on the hall sensor inputs). lb11873 vreg nc 35 34 33 32 31 30 27 26 25 24 22 21 20 19 gnd2 nc nc nc brsel ph fcs tm fgs ld s/s clk 10 11 12 13 14 15 16 17 18 csd frame ei pwm gnd1 pd fcp hb frame 6 5 4 3 2 1 in3- in3+ in2- in2+ nc out1 7 29 28 nc out2 eo fgfil out3 8 9 23 36 vm v cc in1- in1+ top view in1 in2 in3 i out 1 i out 2 i out 3 high low source sink high low source sink in1 in2 in3 i out 1 i out 2 i out 3
lb11873 no.a0081-6/14 internal equivalent circuit block diag ram and external reference circuit control circuit hall amplifier tsd vreg ld in2+ in2- in3+ gnd1 in3- vreg vm ld tm in1+ in1- driver out1 out2 out3 - + filter pwm osc pwm s/s s/s fgs v cc rf curr lim vreg gnd2 comp pd peak hold cont amp ph fcp - + eo ei vreg v cc clk pll clk brsel brsel csd count csd osc fcs - + fg fgfil hb hb
lb11873 no.a0081-7/14 pin functions pin no. pin description equivalent circuit 2 1 35 out1 out2 out3 motor drive outputs 33 gnd2 output block ground 28 vm motor drive output power supply and output current detection connect a resistor (rf) between this pin and v cc . the output current will be limited to the value i out = vrf/rf. 8 9 6 7 4 5 in1+ in1- in2+ in2- in3+ in3- hall sensor inputs "h" is the state where in + > in-, and "l" is the reverse state. it is desirable that the hall sensor signals have an amplitude greater than 50 mvpp if noise on the hall sensor signals is a problem, connect capacitors between the in+ and in- inputs. 10 hb hall sensor element bias current this circuit is turned off in stop mode. 11 gnd1 control circuit block ground 12 pwm sets the pwm oscillator frequency. connect a capacitor between this pin and ground. a 680pf capacitor sets the oscillator frequency to be about 34khz. continued on next page. vreg 300 4 300 9 7 5 8 6 vreg 10 vreg 2k 200 12 1 2 35 300 vm 33 2 8 v cc
lb11873 no.a0081-8/14 continued from preceding page. pin no. pin description equivalent circuit 13 fcp current limiter circuit frequency characteristics correction connect a capacitor (about 0.01 f to 0.1 f) between this pin and ground. the output duty is determined by comparing the voltage at this pin with the pwm oscillator waveform. 14 pd phase comparator output the phase error is converted to a pulse duty and output from this pin. 15 ei error amplifier input 16 eo error amplifier output 17 fgfil fg filter this pin is normally left open. if noise on the fg signal is a problem, connect a capacitor (about 20pf or smaller) between this pin and ground. continued on next page. vreg 300 13 14 300 15 16 17 vreg vreg 300 vreg 40k vreg 300
lb11873 no.a0081-9/14 continued from preceding page. pin no. pin description equivalent circuit 18 csd initial reset pulse generation and protection circuit reference oscillator connect a capacitor between this pin and ground. 19 fgs fg schmitt trigger output 20 ld phase lock detection output this output goes to the on state (low-level output) in the phase locked state. 21 s/s start/stop control low : 0v to 1.0v high : 2.0v to vreg hysteresis : about 0.25v this pin goes to the high level when open. a low level specifies the start state. 22 clk clock input low : 0v to 1.0v high : 2.0v to vreg hysteresis : about 0.25v f clk = 10khz max. if there is noise on this signal, insert a noise rejection capacitor at this input. continued on next page. vreg 300 18 19 20 5k vreg vreg 5k 21 vreg 20k 30k vreg 20k 22 30k
lb11873 no.a0081-10/14 continued from preceding page. pin no. pin description equivalent circuit 23 brsel deceleration (braking) control selection low : 0v to 1.0v high : 2.0v to vreg this pin goes to the high level when open. a low level selects reverse torque control and a high level selects free running braking. if reverse torque control is used, an external schottky barrier diode will be required on the low side of the output. 24 ph rf waveform smooth connect a capacitor between this pin and ground. 25 fcs control loop frequency characteristics correction connect a capacitor between this pin and ground. 26 tm monitor output this pin is normally left open. continued on next page. vreg 20k 5k 23 30k vreg 500 34 25 vreg 300 vreg 300 26
lb11873 no.a0081-11/14 continued from preceding page. pin no. pin description equivalent circuit 27 vreg stabilized power supply output (5v output) connect a capacitor between this pin and ground for power supply stabilization. (about 0.1 f) 29 v cc power supply. connect a capacitor (a few tens of f or larger) between this pin and ground so that noise does not enter the ic. 3, 30 31, 32 34, 36 nc since this pin is not connected internally to the chip, it can be used for wiring connections. frame connect this pin to ground. lb11873 overview 1. speed control circuit since the lb11873 adopts pll speed control, it provides pr ecise, low-jitter, and stable motor operation. this pll circuit compares the falling edge of the clk signal with the fg signal (edges on which the in1 input changes from low to high and fgs output rising edges) and controls motor operation based on the difference. during control operation, the fg servo frequency is the same as the clk signal frequency. f fg (servo) = f clk 2. output drive circuit this ic minimizes motor vibration and noise by changing the output current smoothly during phase switching. since the change (slope) imposed on the output current during phase switching uses the slope of the hall sensor input waveform, the changes in the output waveforms at phase switching will become too steep if the hall sensor input waveform slope is steep. this will reduce the noise and vi bration reducing effect of this technique. thus care is required concerning the slope of the hall sensor input waveform. low side output transistor pwm switching is used for motor speed control and the drive output is adjusted by changing the duty. the diode between out and vm used for the regene rative current when the pwm is off is built into this ic. due to the parasitic diode between out and ground, if reverse control mode (torque braking) is selected for braking, an external schottky barrier diode must be used. also, if there ar e problems when the output cu rrent is large (for example, incorrect operation or waveform disruption during low side kickback) a schottky barrier diode must be connected between out and ground. note that if it is necessary to reduce ic thermal dissipation du ring constant-speed operation, it may be effective to insert a schottky barrier diode between out and vm. this effect occurs because the regenerative current during pwm switching will be dissipated in the external diode instead of the ic's internal diode. 3. current limiter circuit the current limiter circuit limits the drive current to a cu rrent determined by the equation i = vrf/rf, where vrf = 0.5v (typical) and rf is the current detection resistor. the limiting operation works by reducing other output on duty to suppress the drive current. the current limiter circuit detects the reve rse recovery current due to pwm opera tion and, to assure that the current limiting operation is not performed incorr ectly, provides a delay of about 2s be fore it operates. since the changes in the current levels at startup (the state where there is no counterelectromotive force from the motor) will be rapid if either the motor coil resistance is low or if the inductance is low, there are cases where curr ent limiter will operates at a current level above that set due to this delay. in these cases, it will be n ecessary to take the am ount of current increase due to the delay into account when setting the current limit value. 27 v cc
lb11873 no.a0081-12/14 4. power saving circuit this ic goes into a power saving state in which current drai n is reduced when set to the stop state. this power saving state is implemented by cutting the bias current to most of th e circuits in the ic. the 5v regulator output, however, is still output when the ic is in the power saving state. 5. reference clock care must be taken to assure that no noise due to chattering or other problems appears on the externally input clock signal. while the input circuit is designed with hysteresis, no ise must be rejected by, for example, inserting capacitors in the clock line if noise problems occur. the lb11873 provides a built-in clock disconnection protecti on circuit. at clock frequencie s lower than the frequency determined by the following equation, the lb11873 will no t perform its normal control operation, but rather will operate in an intermittent mode. f (hz) 1.02 ccsd ccsd (f) : the capac itor connected between th e csd pin and ground. if a 0.033f capacitor is used, the frequency will be about 31hz. if the ic is set to the start state with absolutely no clock signal provided, the motor will first start to turn somewhat and then the drive will be turned off. if motor rotation stops, a time in excess of the constraint pr otection operating time elapses, and then the clock signal is applied again, drive operation will not be restarted. however, if the clock signal is reapplied before the constraint protection circuit operates, dr ive operation will restart. 6. pwm frequency the pwm frequency is determined by the capacitance of the capacito r (c) connected to the pwm pin. f pwm 1/(43000 c) if a 680pf capacitor is used, the circuit will oscillate at about 34khz. if the pwm frequency is too low the motor will emit switching noise, and if it is too high the power loss in the output will increase. a frequency in the range 15khz to 50khz is desirable. this capacitor must be connected between this pin and the gnd pin by lines that are as short as possible to make this circuit immune to noise. the capacitor ground side must be connected as close as possible to the ic control block ground (the gnd1 pin), to minimize the influence of the output. 7. hall sensor input signals the hall sensor input signals must have an amplitude (differential) of over 50mvpp. if disruption of the output waveforms occurs due to noise on these signals, capacitors must be connected between the hall sensor inputs (between the + and - sides). 8. fcs pin the capacitor (about 0.1f) connected to the fc pin is required for correction of the control loop frequency characteristics. 9. constraint protection circuit the lb11873 includes a built-in constraint protection circuit to protect the ic and the motor if the motor is physically constrained from turning. if fg signal (one side edge of in1) does not switch states fo r a period in excess of a certain fixed time in the start state, the pwm drive side output is turned off. the time is set by the capacito r connected to the csd pin. set time (seconds) 30.5 0.98 ccsd ( f) if a 0.033f capacitor is used, the protectio n operation time will be about 0.99 seconds. the constraint protection state can be cleared by either switching to the stop state (and remaining for over 100 s) or turning the power off and then on again. note that the constr aint protection circuit may not operate correctly if there is noise on the fg signal when the motor is physically constrained.
lb11873 no.a0081-13/14 10. phase lock signal (1) phase lock range since this ic does not have a speed system counter, th e speed error range in the phase locked state cannot be determined by the ic characteristics alone. (this is because th e range is affected by the ac celeration with changes in the fg frequency.) if it is necessary to stipulate this in conjunc tion with a motor, it will be necessary to measure the range with the actual motor state. sin ce speed errors occur easily in states where th e fg acceleration is larg e, it is thought that the lock pull-in time at startup and the unlock time due to clock switching will be the cases where the speed error is the largest. (2) phase lock signal mask function it is possible to assure that the lock signal is output in stable states by masking the short-term low levels due to hunting during lock pull-in. note, however, that the lock sign al output will be delayed by the amount of the mask time. the mask time is set by the capacitor connected between the cld pin and ground. mask time (s) 6.5 0.98 ccsd ( f) when a 0.033f capacitor is used, the mask time will be about 210ms. if full masking is required, the mask time must be set with an adequate margin. 11. initial reset to apply an initial reset to the logic circuit, the ic goes to the reset state until the csd pin voltage changes from 0v to about 0.63v. after the reset is cleared, drive will start. the reset time can be calculated quite closely with the following equation. reset time (s) 0.13 ccsd ( f) a reset time of over 100s is required. 12. power supply stabilization since this ic is used in switching drive applications w ith large output currents, the power supply line is easily disrupted. therefore it is necessary to connect an adequately large capacitor between the v cc pin and ground. the capacitor ground side is connected to the gnd2 pin, which is the power system ground, and must be connected as close as possible to the pin. if the capacitor (an electrolytic capacitor) cannot be connecte d close to the pin, a ceramic capacitor of about 0.1f must be connected close to the pin. if reverse control mode (torque braking) is selected for brak ing, since there will be states where the current returns to the power supply, the power supply line level will be especially subject to disruption. since the power supply line is most easily disrupted during lock pull-in at high speeds, designers must analyze this case carefully and select an adequately large capacitor. since the power supply line is particularly susceptible to di sruption if a diode is inserted in the power supply line to prevent destruction of the ic by reverse connection, an even larger capacitor must be selected in this case. 13. vreg stabilization connect a capacitor with a value over 0.1f to stabilize th e vreg voltage, which is the ic's control circuit power supply. this capacitor's ground side must be connected as close as possible to the ic's control block ground (the gnd1 pin). 14. error amplifier system components the external components for the error amplifier block must be located as close as possible to the ic to minimize the influence of noise. these components must also be located as far from the motor as possible. 15. frame pin an electrolytic capacitor must be connected between the fr ame pin and gnd2 with the capacitor's ground side is connected to gnd2.
lb11873 ps no.a0081-14/14 on semiconductor and the on logo are registered trademarks of semiconductor components industries, llc (scillc). scillc owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. a listing of scillc?s product/patent coverage may be accessed at www.onsemi.com/site/pdf/patent-marking.pdf. scillc reserves the right to make changes without further notice to any products herein. scillc mak es no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does scillc assume any liability ar ising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequentia l or incidental damages. ?typical? parameters which may be provided in scillc data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. all operating parameters, including ?typicals? must be validated for each customer application by customer?s techn ical experts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorize d for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other appli cation in which the failure of the scillc product could create a situation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indemnify and hold scillc and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of persona l injury or death associated with such unintended or unauthorized use, even if such claim alleges that scillc was negligent regarding the design or manufacture o fthe part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws a nd is not for resale in any manner.

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